@phdthesis{nasser:tel-02516046,
TITLE = {An Efficient Computer-Aided Design Methodology for FPGA\&ASIC High-Level Power Estimation Based on Machine Learning},
AUTHOR = {Nasser, Yehya},
URL = {https://theses.hal.science/tel-02516046},
NUMBER = {2019ISAR0014},
SCHOOL = {INSA de Rennes},
YEAR = {2019},
MONTH = Nov, KEYWORDS = {Power consumption ; Fpga ; Neural networks ; Modeling ; ANN ; Consommation d'{\'e}nergie ; Fpga ; Les r{\'e}seaux de neurones ; ASIC},
TYPE = {Theses},
PDF = {https://theses.hal.science/tel-02516046/file/2019ISAR0014_Nasser_Yehya.pdf},
HAL_ID = {tel-02516046},
HAL_VERSION = {v1},
}